1. Field of the Invention
The present invention relates to a test head for an IC tester, capable of distributing waveform signals to a plurality of devices arranged in parallel without use of a distribution circuit at a measurement test run by use of the IC tester on the plurality of the devices arranged in parallel.
2. Prior Art
FIGS. 2 and 3 are schematic representations illustrating the constitutions of conventional test heads for an IC tester, respectively, for use at a test run on a plurality of devices arranged in parallel.
Firstly, referring to FIG. 2, one of the test heads for the IC tester is described hereafter. The test head 1 in FIG. 2 is provided with a back board 3, with which a plurality of pin-electronics-cards 2 are linked so as to be electrically connected thereto.
The pin-electronics-cards 2 are connected to both the devices under test (hereinafter referred to as DUTs) not shown and the waveform shaper so as to be able to send test signals to DUTs.
Further, the back board 3 is constituted such that a waveform signal shaped at a waveform shaper 4 is split into a plurality of signals via a distribution circuit (not shown) and such signals are fed to the back board 3.
Application of a test signal in an identical waveform to each of the eight DUTs suffices for running a measurement test on, for example, eight DUTs arranged in parallel with use of the single test head 1 constituted as described above. Accordingly, the waveform signal shaped at the waveform shaper 4 is split into eight identical signals through a distribution circuit provided at the outlet of the waveform shaper 4, and then the eight signals are sent to the pin-electronics-cards 2 housed in the test head 1 via the back board 3.
In the case of the test head for the IC tester as shown in FIG. 2, there arises a problem of the need for providing numerous signal lines for connecting the waveform shaper 4 to the test head 1.
Hence, in order to solve such a problem as described in the foregoing, another test head for the IC tester, as shown in FIG. 3, has been proposed. Now referring to FIG. 3, parts corresponding to same in FIG. 2 are denoted by like reference numerals. In addition to the constitution of the test head 1 as shown in FIG. 2, a buffer board 8 is provided inside the test head 1, and a distribution circuit is provided on the buffer board 8 such that the waveform signal shaped at the waveform shaper 4 is split through the distribution circuit of the buffer board 8.
Further, branch cards 7 are interposed between the buffer board 8 and the back board 3. In other respects, the constitution of the test head 1 is the same as that in FIG. 2.
Similarly to the case of the test head shown in FIG. 2, application of a test signal in an identical waveform to each of the eight DUTs suffices for running a measurement test on eight DUTs arranged in parallel with use of the test head for the IC tester shown in FIG. 3. Accordingly, the waveform signal shaped at the waveform shaper 4 is received by the buffer board 8, split into eight identical signals through a distribution circuit provided on the buffer board 8, and then the eight signals are delivered to the pin-electronics-cards 2 via the branch cards 7.